 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| d a t a sh eet product speci?cation supersedes data of 1990 dec 01 2003 jul 25 integrated circuits 74hc08; 74hct08 quad 2-input and gate
2003 jul 25 2 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 features complies with jedec standard no. 8-1a esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. specified from - 40 to +85 c and - 40 to +125 c. description the 74hc/hct08 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct08 provide the 2-input and function. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. for 74hc08: the condition is v i = gnd to v cc . for 74hct08: the condition is v i = gnd to v cc - 1.5 v. function table note 1. h = high voltage level; l = low voltage level. symbol parameter conditions typical unit 74hc08 74hct08 t phl /t plh propagation delay na, nb to ny c l = 15 pf; v cc = 5 v 7 11 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per gate notes 1 and 2 10 20 pf input output na nb ny lll lhl hll hhh 2003 jul 25 3 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 ordering information pinning type number package temperature range pins package material code 74hc08n - 40 to +125 c 14 dip14 plastic sot27-1 74hct08n - 40 to +125 c 14 dip14 plastic sot27-1 74hc08d - 40 to +125 c 14 so14 plastic sot108-1 74hct08d - 40 to +125 c 14 so14 plastic sot108-1 74hc08db - 40 to +125 c 14 ssop14 plastic sot337-1 74HCT08DB - 40 to +125 c 14 ssop14 plastic sot337-1 74hc08pw - 40 to +125 c 14 tssop14 plastic sot402-1 74hct08pw - 40 to +125 c 14 tssop14 plastic sot402-1 74hc08bq - 40 to +125 c 14 dhvqfn14 plastic sot762-1 74hct08bq - 40 to +125 c 14 dhvqfn14 plastic sot762-1 pin symbol description 1 1a data input 2 1b data input 3 1y data output 4 2a data input 5 2b data input 6 2y data output 7 gnd ground (0 v) 8 3y data output 9 3a data input 10 3b data input 11 4y data output 12 4a data input 13 4b data input 14 v cc supply voltage 2003 jul 25 4 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 handbook, halfpage mna220 08 1 2 3 4 5 6 7 8 14 13 12 11 10 9 1a 1b 1y 2a 2b 2y gnd 3y 3a 3b 4y 4a 4b v cc fig.1 pin configuration dip14, so14 and (t)ssop14. handbook, halfpage 114 gnd (1) 1a v cc 7 2 3 4 5 6 1b 1y 2a 2b 2y 13 12 11 10 9 4b 4a 4y 3b 3a 8 gnd top view 3y mce183 fig.2 pin configuration dhvqfn14. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. handbook, halfpage mna222 1a 1b 1y 2 1 3 2a 2b 2y 5 4 6 3a 3b 3y 10 9 8 4a 4b 4y 13 12 11 fig.3 logic symbol. handbook, halfpage mna223 3 & & & & 2 1 6 5 4 8 10 9 11 13 12 fig.4 iec logic symbol. 2003 jul 25 5 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 handbook, halfpage mnb037 a b y fig.5 hc logic diagram (one gate). handbook, halfpage mna221 a b y fig.6 hct logic diagram (one gate). recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. for dip14 packages: above 70 c derate linearly with 12 mw/k. 2. for so14 packages: above 70 c derate linearly with 8 mw/k. for ssop14 and tssop14 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 c derate linearly with 4.5 mw/k. symbol parameter conditions 74hc08 74hct08 unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0 - v cc v v o output voltage 0 - v cc 0 - v cc v t amb ambient temperature see dc and ac characteristics per device - 40 +25 +125 - 40 +25 +125 c t r ,t f input rise and fall times v cc = 2.0 v -- 1000 --- ns v cc = 4.5 v - 6.0 500 - 6.0 500 ns v cc = 6.0 v -- 400 --- ns symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v or v i >v cc + 0.5 v - 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v - 20 ma i o output source or sink current - 0.5v 2003 jul 25 7 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 t amb = - 40 to +85 c v ih high-level input voltage 2.0 1.5 -- v 4.5 3.15 -- v 6.0 4.2 -- v v il low-level input voltage 2.0 -- 0.5 v 4.5 -- 1.35 v 6.0 -- 1.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a 2.0 1.9 -- v i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.84 -- v i o = - 20 m a 6.0 5.9 -- v i o = - 5.2 ma 6.0 5.34 -- v v ol low-level output voltage v i =v ih or v il i o =20 m a 2.0 -- 0.1 v i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.33 v i o =20 m a 6.0 -- 0.1 v i o = 5.2 ma 6.0 -- 0.33 v i li input leakage current v i =v cc or gnd 6.0 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd 6.0 -- .5.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 6.0 -- 20 m a symbol parameter test conditions min. typ. max. unit other v cc (v) 2003 jul 25 8 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 t amb = - 40 to +125 c v ih high-level input voltage 2.0 1.5 -- v 4.5 3.15 -- v 6.0 4.2 -- v v il low-level input voltage 2.0 -- 0.5 v 4.5 -- 1.35 v 6.0 -- 1.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a 2.0 1.9 -- v i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.7 -- v i o = - 20 m a 6.0 5.9 -- v i o = - 5.2 ma 6.0 5.2 -- v v ol low-level output voltage v i =v ih or v il i o =20 m a 2.0 -- 0.1 v i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.4 v i o =20 m a 6.0 -- 0.1 v i o = 5.2 ma 6.0 -- 0.4 v i li input leakage current v i =v cc or gnd 6.0 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd 6.0 -- 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 6.0 -- 40 m a symbol parameter test conditions min. typ. max. unit other v cc (v) 2003 jul 25 9 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 family 74hct08 at recommended operating conditions; voltages are referenced to gnd (ground = 0). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c v ih high-level input voltage 4.5 to 5.5 2.0 1.6 - v v il low-level input voltage 4.5 to 5.5 - 1.2 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a 4.5 4.4 4.5 - v i o = - 4.0 ma 4.5 3.84 4.32 - v v ol low-level output voltage v i =v ih or v il i o =20 m a 4.5 - 0 0.1 v i o = 4.0 ma 4.5 - 0.15 0.26 v i li input leakage current v i =v cc or gnd 5.5 -- 0.1 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd; i o =0 5.5 -- 0.5 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 2 m a d i cc additional supply current per input v i =v cc - 2.1 v; i o =0 4.5 to 5.5 - 60 216 m a t amb = - 40 to +85 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.84 -- v v ol low-level output voltage v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.33 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd; i o =0 5.5 -- 5.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 20 m a d i cc additional supply current per input v i =v cc - 2.1 v; i o =0 4.5 to 5.5 -- 270 m a 2003 jul 25 10 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 t amb = - 40 to +125 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a 4.5 4.4 -- v i o = - 4.0 ma 4.5 3.7 -- v v ol low-level output voltage v i =v ih or v il i o =20 m a 4.5 -- 0.1 v i o = 4.0 ma 4.5 -- 0.4 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd; i o =0 5.5 -- 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 40 m a d i cc additional supply current per input v i =v cc - 2.1 v; i o =0 4.5 to 5.5 -- 294 m a symbol parameter test conditions min. typ. max. unit other v cc (v) 2003 jul 25 11 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 ac characteristics family 74hc08 gnd = 0 v; t f = t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb =25 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 2.0 - 25 90 ns 4.5 - 918 ns 6.0 - 715 ns t thl /t tlh output transition time see figs 7 and 8 2.0 - 19 75 ns 4.5 - 715 ns 6.0 - 613 ns t amb = - 40 to +85 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 2.0 -- 115 ns 4.5 -- 23 ns 6.0 -- 20 ns t thl /t tlh output transition time see figs 7 and 8 2.0 -- 95 ns 4.5 -- 19 ns 6.0 -- 16 ns t amb = - 40 to +125 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 2.0 -- 135 ns 4.5 -- 27 ns 6.0 -- 23 ns t thl /t tlh output transition time see figs 7 and 8 2.0 -- 110 ns 4.5 -- 22 ns 6.0 -- 19 ns 2003 jul 25 12 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 family 74hct08 gnd = 0 v; t f = t f = 6 ns; c l =50pf. ac waveforms symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb =25 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 4.5 - 14 24 ns t thl /t tlh output transition time see figs 7 and 8 4.5 - 715 ns t amb = - 40 to +85 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 4.5 -- 30 ns t thl /t tlh output transition time see figs 7 and 8 4.5 -- 19 ns t amb = - 40 to +125 c t phl /t plh propagation delay na, nb to ny see figs 7 and 8 4.5 -- 36 ns t thl /t tlh output transition time see figs 7 and 8 4.5 -- 22 ns handbook, halfpage mna726 t plh t phl v m v m 90% 10% v m v m ny output na, nb input v i gnd v oh v ol t tlh t thl fig.7 waveforms showing the input (na, nb) to output (ny) propagation delays and the output transition times. 74hc08: v m = 50%; v i = gnd to v cc . 74hct08: v m = 1.3 v; v i = gnd to 3 v. 2003 jul 25 13 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 handbook, halfpage mgk565 pulse generator d.u.t v cc v i v o r t c l 50 pf fig.8 load circuitry for switching times. definitions for test circuit: c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. 2003 jul 25 14 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 package outlines unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.087 0.17 0.02 0.13 050g04 mo-001 sc-501-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. dip14: plastic dual in-line package; 14 leads (300 mil) sot27-1 2003 jul 25 15 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1 2003 jul 25 16 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2 2003 jul 25 17 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index 2003 jul 25 18 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 2003 jul 25 19 philips semiconductors product speci?cation quad 2-input and gate 74hc08; 74hct08 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/03/pp 20 date of release: 2003 jul 25 document order number: 9397 750 11265 |
Price & Availability of 74HCT08DB
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |